3
LTC1686/LTC1687
DC ELECTRICAL CHARACTERISTICS VDD = 5V ±5% unless otherwise noted (Notes 2, 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOL
Receiver Output Low Voltage
IOUT = 4mA, VID = – 300mV
q
0.4
V
IOZR
Three-State (High Impedance) Output
0.4V
≤ VOUT ≤ 2.4V
q
–1
1
A
Current at Receiver
IOZD
Three-State (High Impedance) Output
VOUT = – 7V to 12V
q
– 200
200
A
Current at Driver
CLOAD
Receiver and Driver Output Load Capacitance (Note 4)
q
500
pF
IDD
Supply Current
No Load, Pins D, DE, RE = 0V or VDD
q
712
mA
IOSD1
Driver Short-Circuit Current, VOUT = HIGH
VOUT = – 7V or 10V (Note 5)
q
20
mA
IOSD2
Driver Short-Circuit Current, VOUT = LOW
VOUT = – 7V or 10V (Note 5)
q
20
mA
IOSR
Receiver Short-Circuit Current
VOUT = 0V or VDD (Note 5)
q
20
mA
RIN
Input Resistance
– 7V
≤ VCM ≤ 12V
q
22
k
CIN
Input Capacitance
A, B, D, DE, RE Inputs (Note 4)
3
pF
Open-Circuit Input Voltage
VDD = 5V (Note 4), Figure 5
q
3.2
3.3
3.4
V
Fail-Safe
Time to Detect Fail-Safe Condition
2
s
Time
CMRR
Receiver Input Common Mode
VCM = 2.5V, f = 26MHz
45
dB
Rejection Ratio
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tPLH, tPHL
Driver Input-to-Output Propagation Delay
RDIFF = 54, Figures 3, 5
LTC1686C/LTC1687C q
15
18.5
22
ns
CL1 = CL2 = 100pF
LTC1686I/LTC1687I
q
13
18.5
25
ns
tSKEW
Driver Output A-to-Output B Skew
RDIFF = 54, CL1 = CL2 = 100pF,
500
ps
Figures 3, 5
tr, tf
Driver Rise/Fall Time
RDIFF = 54, CL1 = CL2 = 100pF,
3.5
ns
Figures 3, 5
tZH
Driver Enable to Output High
CL = 100pF, S2 Closed, Figures 4, 6
q
25
50
ns
tZL
Driver Enable to Output Low
CL = 100pF, S1 Closed, Figures 4, 6
q
25
50
ns
tLZ
Driver Disable from Low
CL = 15pF, S1 Closed, Figures 4, 6
q
25
50
ns
tHZ
Driver Disable from High
CL = 15pF, S2 Closed, Figures 4, 6
q
25
50
ns
tPLH, tPHL
Receiver Input-to-Output Propagation Delay CL = 15pF, Figures 3, 7
LTC1686C/LTC1687C q
15
18.5
22
ns
LTC1686I/LTC1687I
q
13
18.5
25
ns
tSQD
Receiver Skew
tPLH – tPHL
CL = 15pF, Figures 3, 7
500
ps
tZL
Receiver Enable to Output Low
CL = 15pF, S1 Closed, Figures 2, 8
q
25
50
ns
tZH
Receiver Enable to Output High
CL = 15pF, S2 Closed, Figures 2, 8
q
25
50
ns
tLZ
Receiver Disable from Low
CL = 15pF, S1 Closed, Figures 2, 8
q
25
50
ns
tHZ
Receiver Disable from High
CL = 15pF, S2 Closed, Figures 2, 8
q
25
50
ns
Maximum Receiver Input
(Note 4)
q
2000
ns
Rise/Fall Times
tPKG-PKG
Package-to-Package Skew
CL = 15pF, Same Temperature (Note 4)
1.5
ns
SWITCHING CHARACTERISTICS
U
VDD = 5V, unless otherwise noted (Notes 2, 3).
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